The next generation of exquisite sensors being developed by the DoD and the IC will provide unparalleled advantages for intelligence surveillance and reconnaissance; however, these sensors produce extraordinary amounts of raw data. The rate of data coming off of these sensors threatens to outpace our capacity to transmit bits to the ground station and overwhelms the on-board memory resources. Consequently, we must consider options for processing raw data on the spacecraft, and distilling that data into actionable information that can be sent to an analyst on the ground, or used by the spacecraft to take autonomous action.

In response, the Air Force Research Laboratory (AFRL) established a dedicated architecture test-bed under the Spacecraft Performance Analytics and Computing Environment Research (SPACER) project. The SPACER lab exists to provide guidance on how to improve the on-orbit processing capabilities of national security space systems by leveraging commercial industry processing technologies such as heterogeneous multi-processor system on a chip architectures for low power mobile phone processors, or neural networks architectures for autonomous vehicle operation and big data analytics.

Currently we seek an applicant with a background in neuromorphic computing. Our research interests center on understanding the suitability of neuromorphic architectures to solve computationally complex image processing applications for the Air Force. The effort will start with an assessment of neural networks instantiated using digital logic, but is expected to evolve toward a cortical processing approach. Cortical processing is distinguished from neuromorphic processing by the following features: online “continuous” training, hierarchical memory architecture, and a feedback between input sensor and the neural substrate. A detailed assessment of the energy and performance consequences of a digital CMOS implementation versus neuromorphic or cortical implementation of an image processing algorithm is desired. The specifics of the algorithms under consideration will be given at a later date.  The SPACER architecture test-bed allows researchers to address the increasing challenge of mapping mission requirements to hardware and software implementations for space computing applications, and provides multiple challenging research opportunities for an enthusiastic applicant.

 

References:

1. Erik P. DeBenedictis, Jesse K. Mee, Michael P. Frank, “The Opportunities and Controversies of Reversible Computing,” IEEE Computer, vol. 50, no. 6, pp. 76-80 (2017) 

2. J. Lyke, J. Mee, A. Edwards, A. Pineda, E. DeBenedictis and M. Frank, "On the energy consequences of information for spacecraft systems," 2017 IEEE International Conference on Wireless for Space and Extreme Environments (WiSEE), Montreal, QC, Canada, pp. 104-109 (2017)

3. Jesse Mee, Andrew Pineda, Reed Weber, Phillip Cunio, and Keith Avery, “Architecture Investigation for Future Space Processing,” Hardened Electronics and Radiation Tech. Conf., Monterrey, California (2016)

4. A. C. Pineda, J. K. Mee, R. Webber and P. Cunio; “Benchmarking Image Processing for Space: Introducing the SPACER Architecture Laboratory,” IEEE Aerospace, Accepted, Big Sky, Montana (2016)

 

 

 

key words

Spacecraft; Embedded System; Machine Learning; Artificial Intelligence, Neuromorphic, Architecture; Optimization;

Citizenship:  Open to U.S. citizens

Level:  Open to Postdoctoral and Senior applicants