This research focuses on developing semiconductor materials for the next generation of infrared detectors. We need a theorist to advance the state-of-the-art in infrared materials and device modeling. HgCdTe is the material of choice for long-wave infrared (LWIR: 8-12 μm) detectors and very long-wave infrared (VLWIR: 12-15 μm) detectors. In the current state-of-the-art the LWIR and VLWIR HgCdTe epilayers are deposited on lattice matched CdZnTe substrates. These substrates are expensive, only available in small sizes, very brittle, can break easily, and have poor thermal match with the focal plane arrays (FPAs) silicon readout circuitry.

In order to solve this problem, silicon is used as an alternate substrate. The advantages of silicon substrates include their low cost, large format (increases production yield), compatibility with standard processing equipment, good mechanical strength, and excellent thermal match to silicon readout circuitry. However, a 19 % lattice mismatch exists between the silicon substrate and the HgCdTe epilayer. To mitigate the effect of lattice mismatch on the crystallinity of the HgCdTe epilayer, buffer layers of II-VI materials are deposited on the silicon substrate. The buffer layer process starts with monolayer arsenic coverage on the silicon substrate followed by a thin layer (a few atomic layers thick) of ZnTe. Approximately 10 μm of CdTe is deposited on the ZnTe. The HgCdTe epilayer is then deposited on the II-VI buffer layer.

The buffer layer process significantly improves the crystallinity of the HgCdTe epilayer (with double crystal x-ray rocking curve full width at half maximum values as low as 60 arc-seconds). However, the dislocation density of HgCdTe epilayers deposited on buffer layer/silicon is still ≈ 1×10⁷cm^-2. For mid-wave infrared (MWIR: 3-5 μm) HgCdTe/Si photo-detectors, lattice mismatch does not limit tactical device performance. However, in LWIR and VLWIR HgCdTe epilayers deposited on silicon, high dislocation density results in low photo-detector quantum efficiency and operability. The mechanisms causing the high dislocation density and mitigating their impact on electrical performance needs to be examined and understood.

The challenge is to deposit LWIR and VLWIR HgCdTe epilayers on silicon and preserve the photo-detection capability. A more detailed examination of HgCdTe epilayers on silicon is required. The silicon substrate-buffer layer and buffer layer-HgCdTe interface need to be investigated in detail. A material studio modeling program will help us to understand HgCdTe growth on silicon. The complexity of these structures requires the use of high-performance computing. These models can aid in the fundamental understanding of defect generation resulting from the large lattice mismatch of HgCdTe on silicon deposition. This examination should allow the scientist to determine methods to mitigate the high dislocation density. Results from the modeling programs can be replicated experimentally at NVESD. We have molecular beam epitaxy systems with the capability of producing buffer layers and HgCdTe epilayers deposited on silicon substrates. Experimental measurements from these layers will be fed back into the modeled results. Epilayers will be characterized to iteratively improve modeling results. Modeling, growth, and measurement will be iterated until a better understanding of defect formation in LWIR HgCdTe-on-Si is obtained.

An Associate will be given the opportunity to advance the simple model of HgCdTe currently used. This work should advance the state-of-the-art in solid-state physics modeling of HgCdTe and contribute to the mission of a team of scientists working on a closely coupled program.