RAP opportunity at National Institute of Standards and Technology NIST
Solid-State Device Reliability and Resiliency
Location
Physical Measurement Laboratory, Nanoscale Device Characterization Division
opportunity |
location |
|
50.68.03.B8389 |
Gaithersburg, MD 20899 |
NIST only participates in the February and August reviews.
Advisers
name |
email |
phone |
|
Jason P Campbell |
jason.campbell@nist.gov |
301.975.8308 |
Jason T Ryan |
jason.ryan@nist.gov |
301.975.4446 |
Description
Advanced nanoelectronic solid-state devices are the building block of modern society. The reliability or resiliency of these advanced devices is unfortunately the black swan issue (the most difficult and under-addressed). While reliability is less troubling to many modern consumer electronics like smart phones, it represents a serious threat to automotive, high-performance computing, and medical electronics industries. In these robust applications, high reliability is non-negotiable. Consequently, there is a gigantic research effort to understand and further examine the reliability physics governing device failure with an eye towards accurate end of life prediction. Unfortunately, the constant incorporation of new materials and device geometries quickly negates many established reliability evaluations. The goal of this project is to develop electrical test methodologies to meet this striking challenge.
Understanding the defect physics which govern device reliability requires innovative electrical measurements tailored to specific devices and their intended circuit application. This tall order is accomplished by blending established electrical device measurements with a variety of novel ultra-fast electrical characterizations. This combination of measurements can be used to mimic specific device circuit environments and more readily discern the dominating device reliability physics. Scientifically interesting device structures for this project span everything from exotic transistor structures with exotic materials to resistive random access memories. The main intention is to develop the microscopic models needed to predictively describe device operation and reliability.
References
Vaz CI, et al: “Observation of Strong Reflection of Electron Waves Exiting a Ballistic Channel.” AIP Advances 6: 065212, 2016
Ryan JT, et al: “Frequency Modulated Charge Pumping with Extremely High Gate Leakage.” IEEE Transactions on Electron Devices 62: 769-775, 2015
key words
Device reliability; Transistor; Defects; Device-level jitter; Resistive memory; Fast-IV; Fast-CV Charge pumping; Magnetoresistance;
Eligibility
Citizenship:
Open to U.S. citizens
Level:
Open to Postdoctoral applicants
Stipend
Base Stipend |
Travel Allotment |
Supplementation |
|
$82,764.00 |
$3,000.00 |
|
|