Strain effects material performance in many ways, particularly in semiconductors.  Conventional (CMOS) transistors are manufactured with strain engineered into the channel to improve carrier mobility while residual strains from manufacturing processes can lead to mechanical failures.  Similarly, quantum computing architectures use engineered strains to achieve more desirable band structures but are also subject to large strains from coefficient of thermal expansion mismatches between the fabrication temperatures and the cryogenic operational temperatures.  In these examples, being able to accurately measure the strain with spatial resolution below 10 nm is essential, which remains a substantial technical challenge.  NIST works with semiconductor manufactures to benchmark commercial and in-house strain measurement methods on industrially relevant samples, as well as developing reference materials to allow users of the techniques to evaluate the accuracy of their analyses.

Candidates interested in topics related to this work, please contact us!  The NRC process allows us significant flexibility when defining research goals for NRC fellows.  For example: applying HR-EBSD strain measurement to other classes of materials (e.g. strain in metals, mapping of ferroelectric domains, etc.), using techniques for in-situ studies (e.g. measurement of strain around a crack tip during loading), or maybe comparing techniques (e.g. HR-EBSD of TKD patterns vs. CBED vs. PED vs. 4D-STEM).  We’d love to talk to interested candidates about these or other ideas.

key words

Strain Measurement; High-Resolution Electron Backscatter Diffraction (EBSD); Transmission Kikuchi Diffraction (TKD)

Citizenship:  Open to U.S. citizens

Level:  Open to Postdoctoral applicants